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| AN710 Vishay Siliconix AN710 High-Efficiency Buck Converter for Notebook Computers INTRODUCTION Today, the untethering of electronic equipment has given rise to the need for lightweight power sources and power regulation. Extremely efficient buck converters answer one part of this need. The low losses of these converters eliminate the need for heavy heat sinks and power device packaging. In addition, the energy that is normally consumed by the power converter is available for the application. In this application note, we present a dc-to-dc converter which is intended for use in notebook computers and other portable products. This converter is designed for maximum efficiency, which is made possible by two innovations-lossless current sensing and synchronous rectification. The converter is rated for a load current of 1.5 A and achieves a maximum efficiency of 94% while producing 400 mA at 3.3 V with input voltage of 6 V. The same design was also configured to produce 5 V. 97% efficiency was achieved with input of 6 V, output of 5 V, and output current of 400 mA. The total PCB area is about 2.25 in.2, with a height of 0.25 in. All components except the inductor use surface-mount packages. Furthermore, there are no lead-formed TO-220s or DPAKs, which results in very light weight and small size. Si9150CY IC DESCRIPTION The Si9150CY is a BiCMOS PWM controller IC with all active components necessary for a synchronous buck converter. It is designed to be used with the LITTLE FOOT(R) series of low-voltage MOSFETs. By using higher cell densities (2.5 to 3 million cells per square inch), both the high-side MOSFET switch and the synchronous rectifier (SR) can be housed in a single 8-pin small-outline IC package. While an n-channel MOSFET is the obvious choice for the ground-referenced SR, either p- or n-channel MOSFETs can be used for the high-side switch. N-channel MOSFETs require charge pump and/or bootstrap circuits to generate sufficient gate voltage for channel enhancement. P-channel devices are simple to drive but have higher on-resistance for a given die size. Because of recent improvements in p-channel MOSFET designs, the p-channel approach was chosen for its simplicity. The Si9943 includes a 160-m p-channel and a 100-m n-channel MOSFET in an SOIC-8 package. The Si9150CY controller is housed in a 14-pin SOIC. Since a pin-by-pin description of the Si9150CY is included in its data sheet, we limit this discussion to some interesting details of the functional blocks. FIGURE 1. Si9150CY Block Diagram FaxBack 408-970-5600, request 70583 www.siliconix.com 1 AN710 Vishay Siliconix BREAK-BEFORE-MAKE To prevent shoot-through it is essential to turn off one MOSFET before turning on the opposing MOSFET. The Si9150CY senses the voltages on the N-GATE and P-GATE pins. N-GATE will not be pulled high until P-GATE is within a few volts of VDD. Likewise, P-GATE will not be pulled down until N-GATE is a few volts above GND. The thresholds are determined by using asymmetrical CMOS inverters, i.e., one transistor is significantly larger than the other, so that the logic threshold becomes the gate-to-source threshold of the larger device. There is also a delay while the signal, once enabled, is buffered by the output drivers. This delay is typically 75 to 100 ns. The total deadtime (both MOSFETs off) is equal to about 150 ns. REFERENCE GENERATOR The reference generator is a temperature-compensated bandgap, which is powered whenever the EN pin is high. The output from the bandgap is run through a trimmed voltage divider to an amplifier that can source about 10 mA to the VREF pin. If more than 10 mA is drawn from the amplifier, it will shut down momentarily. The sink current capability is only about 100 A, however. Since the reference has available more than a hundred times as much pull-up as pull-down current, noise on the power pins is effectively rectified. When this happens, either a dc voltage higher than 2.5 V or a relatively low-frequency sawtooth is present on the VREF pin. Since this voltage is used in all parts of the IC, it will not perform to specification if the reference is out of specification. We recommend bypassing the VREF pin with a minimum capacitor value of 0.1 F to ground. CURRENT LIMIT The current limit is a strobed slow-acting comparator which monitors the drain of the p-channel MOSFET. It is triggered when the voltage on the VDD pin minus that on the ISENSE pin is greater than 0.46-V typical, provided that the P-GATE pin has been pulled below about 1.5 V. Once the current limit is triggered, the EN pin is pulled low until the IC shuts down, resetting the dc-to-dc converter and the current limit. The comparator is relatively slow, allowing about 400 ns for the system to settle down after the p-channel MOSFET has turned on. Once the p-channel MOSFET is driven on, it appears in the circuit as a drain-to-source resistance. By using this resistor to sense the current, additional resistors or current transformers are eliminated. This reduces both cost and losses, making it possible to achieve extremely high efficiency. It does, however, restrict the current limit trip point, which is now determined by the MOSFET on-resistance. POWER DOWN The power down section of the IC is a group of load switches and switchable current mirrors. With the EN pin high and the STBY pin low, only the reference generator, the UV lockout, and the pull-up for the STBY pin will operate. With both the EN and the STBY pins high, all other systems are switched on. With EN pulled low, only the EN pull-up resistor consumes power. Under very low load conditions the efficiency of switch mode power converters decreases very rapidly. When it is desirable to operate under light load (<50 mA) for an extended period of time it may be beneficial to implement a linear regulator. With STBY low and EN high, the Si9150CY provides the voltage reference needed for implementation of a linear regulator. DESIGN EXAMPLE OSCILLATOR The oscillator works by applying 2.5 V to the RT pin. The current flowing out of the RT pin is mirrored and fed into the CT pin. When the CT pin reaches 2.5 V, an internal MOSFET pulls the SYNC pin low. The low voltage on SYNC causes the CT pin to be pulled low, resetting the clock. Allowing for small offset voltages, the frequency, f, is 0.9 f = ----------------------------------C OSC x R OSC (1) The dc-to-dc converter shown in Figure 2 is designed especially for use in notebook computers. With a 6-, 8-, or 10cell NiCd battery to power the computer, it is necessary to convert a variable voltage to 5 V and 3.3 V. We assumed the use of two converters, one for each output voltage. This duplication increases the component cost somewhat but allows simple implementation of independent regulation and current limits. A typical computer would use about 500 mA at each voltage, but at times would need up to 1.5 A. While weight and efficiency are optimized, cost effectiveness is also kept in mind. The 5-V converter is considered in depth because, in many respects, it is more difficult to design. In order to reconfigure the resulting converter for a 3.3 V output, it is necessary merely to change R4 to 105 k. where Cosc and Rosc are the capacitor and resistor values tied to the CT and RT pins, respectively. The SYNC voltage is also passed through three inverters to square the edges, and the signal is used to reset the PWM circuitry in the IC. Since the clock resets whenever the SYNC pin is pulled low, two Si9150CYs can be synchronized by connecting their SYNC pins together. If synchronization to an external clock is desired, SYNC should be pulled low for a short period using a 2N7002 or similar MOSFET. The recommended reset pulsewidth is approximately 100 ns. CONVERTER SPECIFICATION The specifications given in Table 1 are representative of a typical portable application. The current limit has been specified fairly loosely, because most applications will permit it and because the lossless current limit circuit requires a wide current limit spread. FaxBack 408-970-5600, request 70583 www.siliconix.com 2 AN710 Vishay Siliconix FIGURE 2. 5-V Synchronous Buck Regulator Schematic TABLE 1. DC-to-DC Converter Specifications Spec Imax ICL Ino load Ishutdown Vin Vout Step-load Output ripple Input ripple Start time Efficiency Operating temp Switching frequency 2.1 4 300 10 5 150 40 300 2 97 25 76 1 94 0 65 50 85 6 4.85 Typ Min 1.5 1.5 Max Unit A Conditions 5.7 8 500 16.5 5.15 300 100 400 5 A mA A V V mV mVrms mVrms ms % C kHz TJ < 150C under fault conditions Iout 10% to 90% Vin = 16.5 V Vin = 16.5 V, Iout = 1.5 A Iout = 0.5 A FaxBack 408-970-5600, request 70583 www.siliconix.com 3 AN710 Vishay Siliconix Ino load is the maximum current that is permissible for the unloaded converter to consume while operating. But this level is too high for a typical computer's shut-down mode, so a linear regulator or small bang-bang converter is assumed to supply power while the computer is shut down. The Ishutdown specification is important during this time. Imax is the current that the load needs to operate. (Actually, this specification is redundant with minimum Icl, but we include it here for clarity.) The maximum current limit trip point must occur at a current that does not cause safety concerns. Likewise, the output voltage must be within the operating voltage requirements of the load. For most 5-V circuitry, this is 5 V 10%. This range must be padded to account for voltage drops and noise generated in the load. The deviation from 5 V can be broken down into dc accuracy, noise, and step-load response. Since, in most designs, the load will not jump from 10% to 90% in a few microseconds, the step-load figure may be divided in half. The load's decoupling capacitors and trace resistances provide an RC filter which smooths the output voltage, allowing the RMS value for output ripple voltage to be used. Thus, the sum of the dc error, half of the step-load response, and the RMS ripple should be less than or equal to about 8% of 5 V. The above explanation is based on rules of thumb and should be scrutinized by the system designer before use. The safest specification uses peak ripple and full step response. Also note that the converter will tend to run a few degrees above the ambient temperature, and it will not be operated while the computer is outside its temperature range. to satisfy safety and system specifications, as well as for inductor design. Finally, the maximum current (ICLtherm) with the MOSFET's junction at its maximum rated temperature is needed to verify the converter's ability to survive a short circuit under worst-case conditions. The current limit will trip if the voltage across the p-channel MOSFET is more than VCL while the MOSFET is fully on. The peak drain current is the sum of the average inductor current and one half the ripple current. Therefore, I V CL I CL = ----------------- - ------------- ripple r DS ( on ) 2 (2) The values of VCL, rDS(on), TJ, and Iripple that are used to calculate each of the current limit ratings are given in Table 2. Unfortunately, the equations for these parameters are nonlinear and interdependent. Therefore, an iterative approach is needed, consisting of the following steps. TABLE 2. Worst-case Parameters as Used for the Current Limit Calculations Type ICLmin ICLmax ICLtherm VCL Min Max Max rDS(on) Max Min Min TJ Max Min Max Iripple Max Min Min DESIGN METHODOLOGY A description of the buck converter design procedure is given here. This particular design employs the Si9150CY driving the Si9943DY complementary half-bridge, but other converters can be designed using the same method. The first step in designing with the Si9150CY is to choose the p-channel MOSFET switch to meet the load current requirements. rDS(on) variations over the spec ranges for voltage and temperature will affect the output current limit trip point, ICL, since rDS(on) is used as the current sensing resistor. Once it is verified that maximum load requirements can be met, the inductor can be designed to meet efficiency and size requirements. In the discussion below, the ripple and power losses are calculated for the surface-mount tantalum capacitors, and some criteria are given for selection of the Schottky diode. An explanation of the feedback network is given, and finally soft-start capacitor selection and board layout considerations are discussed. Begin by estimating TJ = 150C at Vin = 16.5 V and assuming Iripple = 0, so that rDS(on) can be determined. Calculate the power dissipation, including switching and conduction losses. Iterate the calculations to find the correct TJ. Determine the allowable ripple for ICLmin Iout(MAX) = 1.5 A, which yields the minimum value for L. Having found L, use rDS(on) and TJ to verify operation at ICLmin and ICLtherm. Power dissipation comes from two sources--switching losses and conduction losses. The conduction losses are equal to the square of the RMS current times the rDS(on) of the MOSFET. Assuming that the inductor is operating in its linear region and that the converter is efficient, the current running through the p-channel MOSFET is given by equation 3. V in - V out I ripple I P ( t ) = ------------------------ x t + I out - ------------L 2 (3) WORST-CASE CURRENT LIMIT CALCULATIONS There are three important current limit values that must be considered when choosing the p-channel MOSFET. First, the minimum current at which the current limit will trip (ICLmin). This value is needed to ensure that the converter will power the load under all conditions. Secondly, the maximum current at which the current limit will trip (ICLmax). This value is needed where Ip(t) is the current through the p-channel MOSFET, Vin is the input voltage, Vout is the output voltage, Iout is converter output current, L is the inductance in Henries, and Iripple is the inductor peak-to-peak ripple current. t is 0 when the p-channel MOSFET turns on and, t is Iripple times L divided by the quantity Vin - Vout when the MOSFET turns off. The RMS current through the MOSFET (Irmsp) is given by I rmsp = 2 V out I ripple 2 I out + ------------- x ---------V in 12 (4) 4 FaxBack 408-970-5600, request 70583 www.siliconix.com AN710 Vishay Siliconix Conduction loss (Pconp) can now be calculated. V out I ripple 2 P conp = r DS ( on ) x ---------- x I out + ------------V in 12 2 TABLE 3. Calculated Worst-case Current Limits Including Temperature and Ripple Current Effects (5) Spec ICLmin Vin 6V 6V 6V 6V 16.5 V Inductance Large 43 H Large 43 H Large Current 1.62 A 1.53 A 2.89 A 2.76 A 5.6 A Tj 91C 86C 141C 134C N/A Energy lost per switching transition may be approximated by E swp = V in x I P x t f (6) ICLmin ICLtherm ICLtherm ICLmax Here, tf is the equivalent switching time for the MOSFET. A conservative number to use with the Si9943DY is 80 ns. This number will scale with gate charge, qG, if other MOSFETs are used. Including both transitions, switching losses (P swp) can be calculated using equation 7. P swp = 2 x V in x I P x t f x f (7) When used together, the Si9943DY and Si9150CY produce a converter which can be counted on to produce 1.5 A and which will tolerate any overcurrent situation which might arise. For operation above 13.5 VDD a filter (1 k, 33 pF) is needed between the MOSFET drains and the ISENSE pin, refer to Figure 2. INDUCTOR DESIGN where f is the clock frequency. The total power dissipated by the p-channel MOSFET is P p = P conp + P swp (8) Having selected the p-channel MOSFET and determined the ripple current and the minimum current at which the inductor can be fully saturated, the inductor and other power components may be selected. The inductor must meet five criteria: 1. Inductance of more than 43 H 2. Linear while current is in the converter's operating range 3. Not fully saturated at a current of ICLmax 4. Low cost and small size 5. Acceptable efficiency To meet all of these criteria, a conveniently sized core is chosen, and the efficiency of the resulting inductor is checked. If the efficiency is acceptable, the design is done. If not, the inductor's size is adjusted until acceptable efficiency is reached. An approximate size and type of material must be chosen. Usually, either MPP or a power ferrite with an air gap is used in this type of application. In this example, an MPP toroid will be used. The following values are needed-inductance (L), the peak magnetic field at which the core material is linear (Bpk), the peak current at which the inductor is linear (Ipk), the core equivalent length (le), the core equivalent cross section (Ae), and the available core permeability values. Using cgs units, the inductance is 4 x x Ae x N -9 L = -------------------------------------- x 10 le 2 To calculate allowable Iripple, the ICLmin specification must be recalculated using the calculated value for TJ. Using Tj = Pp R thJA + T a (9) the equations for Pp, frequency (76kHz), and the graph of normalized rDS(on) versus TJ, an estimated TJ may be calculated. Here Ta, the ambient temperature, is 50C, and Rthja, the junction-to-ambient thermal resistance, is assumed to be 62.5C/W. After a couple of iterations, TJ is 90.7C and ICLmin is 2.02 A. This allows a maximum Iripple of 1.0 A. Using the equation for Ip(t) above, ( V in - V out ) x V out I ripple = ---------------------------------------------f x L x V in (10) Therefore, this ripple current corresponds to an inductance of 43 H with the worst case Vin = 16.5 V. Now that the limits of the ripple current are known, the survivability of the converter can be checked for rDS(on) values corresponding to both Vin = 6 V and Vin = 16.5 V. Using equation 9 for TJ and the graph of rDS(on) versus TJ, the actual TJ and ICLtherm are calculated. (11) FaxBack 408-970-5600, request 70583 www.siliconix.com 5 AN710 Vishay Siliconix where is 3.14 and N is the number of turns. Also, using the following relationships, N n = --le (12) m R W = 0.839 --------- x 48 cm = 40 m cm (18) The resistance of the inductor wire equals the wire length times its resistance per unit length, which for 25 turns of 24gauge copper wire is 4 x x n x I pk H pk = ----------------------------------10 (13) Next the wire losses (Pwire) in the inductor can be calculated. Since the converter will typically run at less than 1 A, Iout has been set to 1 A. P wire = I rms x R W = 40 mW 2 B pk = -------H pk (19) (14) the maximum value of can be determined from A e x l e x B pk -7 MAX = ------------------------------------- x 10 2 4 x L x x I pk 2 or about 0.8% of the output power. Finally, core losses are calculated. The ripple in the B field (B) is given by (15) ( V IN - V OUT ) x V OUT 8 B = ------------------------------------------------------ x 10 f x N x Ae x V IN (20) A Magnetics Inc. MPP core size of 55040 is larger than necessary, so the 55290 size is checked. Under normal operation the inductance should remain constant, so use Ipk = 3 A. Since MPP has a soft saturation characteristic, it may be used aggressively, and Bpk = 5500 gauss is chosen. If a ferrite is used, Ipk = 5.7 A and the ferrite's Bsat at 150C would be used to prevent complete saturation under worst-case conditions. The gap can be adjusted to give the desired equivalent permeability. An ungapped ferrite should not be used. The 55290 core has Ae = 0.095 cm2 and le of 2.18 cm. Plugging these numbers and 43 H into the above equation, max is 131. Referring to the catalog, 125 is the next lower permeability available. Using the above equations, 10 x I e x B pk N ----------------------------------4 x x x I pk (16) Substituting Vin = 10 V (the input voltage at which the inductor voltage is a symmetric square wave), B = 1,238 gauss. Using the equation supplied by the core vendor, the loss is P core = 0.489 x 10 -11 x 0.0039 x f i.28 B x ------ 2 2.14 (21) or 37 mW. Although this number is not exact, it is evident that core losses are not a problem. The total loss due to the inductor is about 1.5% of the output power-small enough for this application. CAPACITOR SELECTION If the load and source capacitances are ignored, the minimum capacitance and maximum ESR values are obtained, which may be used for conservative design. Such an approach leads to overdesign. Instead, the input capacitor was chosen to avoid significant losses or voltage drop, and the input and output capacitor ESR values are assumed to be halved by the power source and load capacitors. 33-F, 20-V and 47-F, 10-V tantalum capacitors are checked for the input and output filters. Three capacitors are paralleled for the input, and two for the output. After halving, the maximum rated ESR for AVX surface-mount capacitors are 166 m and 225 m for the input and output, respectively. Although the ripple voltage is usually the limiting factor, the power dissipated in the capacitors will be discussed first. The current flowing through the input capacitor (Icap) is I cap ( t ) = I P ( t ) - I P ( t ) (22) If = 125, N is less than 25.4 turns. Using a 55290 core with 25 turns and the equation for L above, L is 42.7 H. Since there is some leeway in the ICLmin specification, this value is acceptable. Now, losses in the inductor are calculated. While the pchannel MOSFET is on, the current in the inductor is the same as the current through the p-channel MOSFET. When the MOSFET is off, the current ramps back down to the same level as at t = 0. Thus, the inductor RMS current (Irmsi) can be calculated as I rmsi = 2 I ripple I out + ---------------12 2 (17) 6 FaxBack 408-970-5600, request 70583 www.siliconix.com AN710 Vishay Siliconix where IP(t) is the current through the p-channel MOSFET and IP(t) is the average input current. The input capacitor RMS current (Irmsci) is I rmsci = I P ( t ) - IP ( t ) 2 2 Since the input ripple is somewhat harder to calculate, the input current is assumed to be larger than Iripple. Under these conditions, I ripple V pkii = ESR in x I out + ------------2 (31) (23) or 2 V out V out 2 2 I ripple 2 I rmsci = I out + ---------------- x ---------- - ------------- x I out 2 V in 12 V in and (24) V out V out 1 1 -V pkqi = ------- x -- x 1 - ---------- x I out x ---------V in C in f V in (32) Now, the power dissipated by the input capacitor can be calculated by using the capacitor ESR. P ci = ESR in I 2 rmsci (25) With ESRin = 166 m, Vin = 10 V, Vout = 5 V, and Iout = 1 A, the power dissipated is 59 mW (or 1.2% of the converter's output power). Likewise, the RMS current through the output capacitor (Irmsco) is I rmsco = 1 ----- x I ripple 12 (26) where Vpkii in the input ripple's ESR component and Vpkqi is the input ripple's capacitive component. Using worst-case conditions for the input and output ripple voltages (Vin = 16.5 V, Iout = 1.5 A, ESRout = 200 m, and Cout = 100 F), Vrmsio is 69 mV. Comparing the peak-to-peak ESR and capacitive ripples, respectively 238 mV and 69 mV, the capacitive component will not add enough voltage to make the RMS ripple exceed 80 mV. This is a high number, but still less than specified. A similar analysis of the voltage across the input capacitor reveals an expected RMS voltage at the input of less than 140 mV. SCHOTTKY DIODE A Schottky diode is included in the circuit to prevent the internal diode of the n-channel MOSFET from turning on. The internal MOSFET should remain off for two reasons. First, being a silicon p-n diode, it has a reverse recovery charge that will cause an effect similar to shoot-through. To estimate these losses, the reverse recovery charge should be multiplied by the input voltage and the converter clock frequency. The charge can be estimated as 130% of half of the di/dt times the reverse recovery time squared. In this converter, with Vin = 16.5 V and Iout = 1.5 A, the loss would be about 130 mW or 2%. Note that while the n-channel MOSFET is causing this power loss, heat is generated in the p-channel MOSFET. The second reason that the Schottky is included is that it has a lower forward drop than the n-channel MOSFET internal diode. The Schottky diode conducts while both MOSFETs are off. During normal operation, this period totals about 300 ns per cycle. During a current limit caused by a very low load resistance, the inductor may completely discharge though the Schottky. The Schottky will generate much less heat than the MOSFET diode while the inductor is discharging. The Schottky should be chosen so that its forward drop is less than the forward drop of the n-channel MOSFET internal diode at ICLtherm. This selection will prevent the additional heat from reverse-recovery charge from overheating the p-channel MOSFET during a high current condition. and the power dissipated is P co = ESR out I 2 rmsco (27) Under the same conditions used for the input capacitor power calculation above, Pco is 21 mW or 0.4%. Now the input and output voltage ripple will be considered. Voltage ripple is caused by two effects, capacitor ESR times the ripple current, and the charge transfer divided by the capacitance. V pkio = ESR out I ripple (28) and V RMSIO = ESR out I RMSCO (29) where Vpkio is the peak-to-peak output ripple voltage and Vrmsio is the RMS output ripple voltage, both due to the output capacitor ESR. The peak-to-peak ripple voltage due to capacitance (Vpkqo) is 1 - I ripple 1- 1 V pkqo = ---------- x -- x ---------- x ------------2xf 2 C out 2 (30) FaxBack 408-970-5600, request 70583 www.siliconix.com 7 AN710 Vishay Siliconix FEEDBACK NETWORK DESIGN A high-efficiency converter requires an output filter with low losses (a high Q). The fast 180-degree phase shift and large increase in gain at the filter resonant frequency complicate the design of the feedback network. For purposes of this discussion, the converter will be simplified to the behavioral model shown in Figures 3 and 4. The gain and phase of the output filter are given in Figure 5. FIGURE 3. The Actual Circuit FIGURE 4. Behavioral Model for Feedback Loop Analysis FIGURE 5. Output Filter Response 8 FaxBack 408-970-5600, request 70583 www.siliconix.com AN710 Vishay Siliconix At low frequencies, the impedance of the inductor is small while the impedance of the capacitor is large, causing the output voltage to be about the same as the input voltage. At high frequencies, the inductor controls the current reaching the capacitor. The current through the inductor lags the input voltage by 90 degrees. Likewise, the voltage across the capacitor lags the current through the inductor by 90 degrees. Therefore, since the output voltage lags the input voltage by 180 degrees, the voltage is actually inverted by the filter. Two approaches may be used for compensation of the buck converter power stage. Figures 6 and 7 show the lowperformance (integrator) compensation method. The circuit values corresponding to these plots are as follows: R1 = 150 k, C1 = 0.01 F (R2, R3, C2, and C3 are not used). By using a dominant low-frequency pole the loop gain can be reduced to 0 dB at a frequency substantially below the filter resonant frequency. This results in a slow dynamic response. To obtain better performance, the gain of the converter must be greater than one at the resonant frequency. We can achieve this improvement by designing the feedback circuit to differentiate, rather than integrate, near the resonant frequency. This approach, which is referred to as a lead-lag network, was used for the compensation of the buck converter. Figures 8 and 9 give the Bode plots for the feedback network and the total loop gain for the circuit values given in Figure 2. FIGURE 6. Low-performance Feedback Network Transfer Function FIGURE 8. High-performance Feedback Network Transfer Function FIGURE 7. Open-loop Gain for the Converter with Low-performance Feedback Network FIGURE 9. Open-loop Gain for the Converter with High-performance Feedback Network FaxBack 408-970-5600, request 70583 www.siliconix.com 9 AN710 Vishay Siliconix DYNAMIC RESPONSE LIMITATIONS Synchronous operation of the converter ensures that the inductor flux is not left at zero, since the inductor current can flow in the reverse direction. Thus the converter runs in continuous conduction mode at all times. The minimum excursion of the output voltage which can be theoretically achieved in continuous conduction is limited by the output filter components. Assuming an ideal feedback network, the controller responds to a step increase in load by immediately applying full voltage, Vin, to the output filter. Also assume that the output filter and switching circuit are lossless. Thus, using the behavioral model in Figures 3 and 4 with both resistors set to 0 and solving for Vout, the following equations are obtained: d V in - V out ( t ) = L x C x ------- x V out ( t ) 2 dt 2 Thus, for any given inductor, there is a minimum capacitor which must be used to achieve a given step response. This value should be padded by a factor of two if a highperformance compensation circuit is to be used. If a lowperformance compensation circuit is to be used, the size of the capacitor will be even larger. The error amplifier has a few characteristics which limit the feedback loop as well. First, the open loop gain is typically 75 dB. This is represented by a pole where the feedback network with an ideal op amp would reach a gain of 75 dB. Secondly, the op amp can source only about 1 mA. At a frequency and amplitude where more than 1 mA is required to keep the feedback pin at the reference voltage, the network will begin to resemble a wire, instead of an integrator. This should happen well above the unity gain crossover frequency of the control loop. Finally, the op amp has a limited gain bandwidth, as illustrated below in Figure 10. (33) V ex ( t ) = V out ( t ) - V out ( 0 ) (34) V ex ( 0 ) = 0 (35) - I step d ---- V ex ( t )l o = ------------dt C (36) 2 V in - V out d ------- V ex ( t )l o = -----------------------2 CxL dt (37) Solving equation 37 yields - I step x sin ( x t ) V ex ( t ) = --------------------------------------------- + Cx [ V in - V out ( 0 ) ] [ 1 - cos ( wt ) ] FIGURE 10. Error Amplifier Bode Plot SOFT-START CAPACITOR SELECTION (38) where = 1 ------------LxC (39) Vex(t) is at an extreme at tm as given by tm - I step -1 tan ----------------------------------------------------------C x x [ V in - V out ( 0 ) ] = ----------------------------------------------------------------------------- (40) After the current limit has been triggered, the following sequence of events occurs. First, the EN and SS pins are pulled low by the current limit circuitry. Once the EN pin has shut off the Si9150CY, both Si9943DY MOSFETs are off. The EN resistor pulls up the EN pin at a rate determined by the EN capacitor (C6 = 180 pF). Once EN passes its threshold voltage, the reference and the current source for the STBY pin are activated. After STBY passes its threshold, the current for RT and the feedback circuitry are turned on. After one clock cycle, the PWM circuitry is activated. Meanwhile, the error amplifier output is restricted to about 0.6 V above the SS voltage. Now the SS voltage ramps up, allowing the COMP voltage to increase. During this period, the converter output voltage will ramp up at a rate of approximately Vin/2.5 times the ramp rate of the SS voltage. 10 FaxBack 408-970-5600, request 70583 www.siliconix.com AN710 Vishay Siliconix LAYOUT CONSIDERATIONS For stable PWM operation and reliable current limiting (i.e., no false trips), it is necessary to use bypass capacitors for the Si9150CY and to lay out the grounds properly. Also, for high-efficiency the high-current traces should be made wide to minimize parasitic losses. These layout-related topics are covered here. The lossless current sense circuit uses the VDD pin as its reference. Therefore, the VDD pin of the Si9150CY should be tied directly to the source of the p-channel MOSFET. Since there is switching noise on the source of the p-channel MOSFET, the ground should be broken into logic ground and power ground as shown in Figure 12. The bypass capacitor for the Si9150CY should be tied to the logic ground. The connection between the power and logic grounds should be much longer than the VDD to p-channel source connection. As a result, the logic ground will track spikes on the p-channel source rather than the n-channel source. Of course, all the signal components, including the feedback network, should be referenced to the logic ground. Figure 12 also shows the ac current paths. The most critical loop is defined by C9, the p-channel MOSFET, and the nchannel MOSFET in parallel with D1. This loop should be kept very short to keep its resonant frequencies high, so that it will not be excited by the switching of the p-channel MOSFET. There are two high-current dc paths whose trace resistances should be minimized, as shown in Figure 13. The figure also shows the RMS currents which must be carried by the input and output filter capacitors. FIGURE 11. Startup Waveforms for Vin = 8.2 V, RLOAD = Since the SS pin is pulled up by 25 A (typical), the current needed to charge the output capacitor (Istartup) is V in 25 x 10 I startup = C out x ------- x -----------------------C ss 2.5 -6 (41) where Css the value of the soft start capacitor in Farads. Istartup should be limited to a value low enough so as not to trigger the current limit when combined with the load that the converter will see initially. FIGURE 12. Ground Layout and High-frequency Bypassing FaxBack 408-970-5600, request 70583 www.siliconix.com 11 AN710 Vishay Siliconix CONCLUSION Cost-effective and small dc-to-dc converters with greater than 90% efficiency no longer require exotic technologies. Figure 14 plots the efficiency versus load current for the converter design described above. Peak efficiency of 97% is achieved at Vin = 6 V and Iout = 400 mA. Over a broad range of line and load conditions the efficiency exceeds 90%. The converter efficiency was also measured for 3.3-V output (change R4 from 33.2 k to 105 k), as shown in Figure 15. Peak efficiency is 94% at Vin = 6 V and Iout = 400 mA. For both the 3.3-V and 5-V cases, the efficiency is reduced as Vin increases. This reduction is due mainly to increased switching and inductor core losses and indicates that six NiCd or NiMH cells should be used for maximum efficiency . The Si9150CY control IC integrates all of the required control functions for a synchronous rectified buck converter-including lossless current sensing, break-before-make timing, and PWM control functions. When driving the Si9943DY MOSFET half-bridge, an all surface-mount, 1.5-A buck regulator occupies only 2.25 square inches of circuit board. Input Capacitor RMS Current = V out 1 I2 - ----- I 2 --------- out 12 ripple V in Output Capacitor RMS Current = I ripple ------------12 2 FIGURE 13. DC Current Paths FIGURE 14. 5-V Output Buck Regulator Measured Efficiency FIGURE 15. 3.3-V Buck Regulator Measured Efficiency 12 FaxBack 408-970-5600, request 70583 www.siliconix.com |
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